The present invention relates to the distribution of clock signals to various points on a semiconductor device, such as a large scale integrated (LSI) circuit, and more particularly, the present invention relates to the use of optimal length transmission lines in the distribution of such clock signals.
A system clock signal is often used by digital circuitry, such as digital circuitry implemented using an LSI circuit, to synchronously execute certain logic functions. For example, microprocessors employ digital circuitry that use system clock signals to synchronously execute logic functions. Microprocessors may operate at system clock frequencies of 1 GHz or more. The system clock signal of a given LSI circuit is often split into many paths to service many different portions of the digital circuitry. Ideally, the system clock signals at different portions of the digital circuitry exhibit exactly the same timing characteristics so that the different portions of the digital circuit operate in exact synchronization. In practice, however, the system clock signals at various points throughout the digital circuitry exhibit different timing characteristics, such as differing rising and/or falling edges, differing duty cycles, and/or differing frequencies. These non-ideal characteristics are often referred to as clock jitter and clock skew.
Clock jitter relates to the inaccuracies inherent in generating the system clock signal. The non-ideal characteristics of the system clock signals due to clock jitter affect all portions of the LSI circuit in the same way, irrespective of how the system clock signals are distributed to those portions of the circuit. Clock skew relates to the inaccuracies introduced into the system clock signals by the distribution technique employed to split the system clock into many paths and deliver the clock signals to different portions of the digital circuit.
Clock signals are conventionally distributed to various portions of the digital circuitry using signal wires. The signal wires, which may be formed of a metal such as copper or aluminum, have inherent, non-ideal properties associated with them. These properties include, for example, inductance, capacitance, resistance, impedance and conductance. These properties can affect how much power is dissipated when signal currents flow through a signal wire. The rise and fall times of the clock signal can also be affected by these properties. Indeed, a clock signal is not an ideal step signal. Rising and/or falling edges (i.e., transitions) of system clock signals are used to provide timing for the digital circuitry. The rise time is the time it takes for a rising edge of a clock signal to transition from a low value to a high value. Similarly, the fall time is the time it takes for a falling edge of a clock signal to transition from a high value to a low value. The rise (or fall) time is referred to herein as Trf.
In general, a clock signal wire dissipates power in accordance with the following equation: C*Vdd2*f, where C is the total capacitance for the signal wire and buffers on either end of the wire, Vdd is the power supply voltage for the clock distribution system, and f is the clock frequency. During Trf, the wire capacitance is pre-charged or discharged, and much of the power lost by the clock signal is dissipated during these transition times.
At high clock frequencies, such as 1 GHz or more, a significant fraction of the power of the clock signal is dissipated during clock distribution. The use of narrow pulses (i.e., pulses with short Trf times) may theoretically address this problem because less power should be dissipated during clock signal distribution. To date, however, the results of using of narrow pulses has not been satisfactory (and therefore not optimally exploited) for on-chip clock signaling because the shapes of narrow pulses may be distorted during transmission along the signal wire.
One method of reducing pulse distortion is to implement the signal wires using transmission lines. This permits the use of narrow clock signal pulses. A transmission line is a transferring medium and structure for an electromagnetic wave, employing one or more signal conductors and one or more ground conductors, in contrast to a typical signal wire that includes a single conductor. Unlike a typical signal wire, a signal on a transmission line propagates as an electromagnetic wave with a velocity that does not depend on, for instance, the inductance, the capacitance, the resistance and/or the conductance of the transmission line. Because these parameters may shape the attenuation of the electromagnetic wave, a narrow clock pulse propagated on an ordinary signal wire may be distorted and/or dissipated whereas the same pulse propagated on a transmission line may not be so affected. Even though the distortion of narrow pulses is reduced when a transmission line is employed, clock signals can be adversely affected by the length of the transmission line and how the line is split into branches.
Transmission lines may be used to address the problems associated with clock jitter and clock skew; however, in order to achieve this, a transmission line should be carefully designed. Preferably, the transmission line should be as straight as possible, as any bend in the line can cause change in wire impedance, which in turn may cause a reflection of the clock signal. Unfortunately, the distribution paths providing clock signals to different portions of a digital circuit are rarely straight. A solution to this problem is to place repeater buffers along the transmission line at points where the line bends. Buffers act to regenerate clock signals and provide uniform delay across the digital circuitry.
The clock signal transmitted from a first buffer to a second buffer along a signal line is called an incident wave. Each buffer has an input for receiving the incident wave and an output. The impedance of each input and output should be carefully matched with the impedance of the transmission line in order to avoid ringing. For example, ringing occurs when an incident wave propagates along the transmission line from the output of the first buffer to the input of the second buffer, and a mismatch in impedance at the input of the second buffer results in a portion of the incident wave being reflected, which is called a first reflected wave. The first reflected wave travels back from the input of the second buffer to the output of the first buffer. Further ringing occurs when an impedance mismatch at the output of the first buffer results in a portion of the first reflected wave being reflected, which is called a second reflected wave. The second reflected wave travels from the output of the first buffer to the input of the second buffer. This ringing repeats until the power of the reflected waves is dissipated.
Unfortunately, the results of using transmission lines in clock distribution on an LSI circuit have been unsatisfactory because, among other problems, ringing has been common and efforts to eliminate such ringing have been unsuccessful. Indeed, ringing has caused loss of signal propagation through buffer stages and has even caused damage to the buffer stages thereby rendering the digital circuitry at least partially inoperable. Accordingly, there is a need for a new clock distribution method and apparatus that addresses the ringing problem, as well as other problems, particularly in an LSI application.
In accordance with one or more aspects of the present invention, an integrated circuit, includes a first clock distribution buffer having an input node and an output node, the first clock distribution buffer being operable to produce an incident signal at the output node thereof from an input signal at the input node thereof; a transmission line having first and second ends defining a length, the first end being coupled to the output node of the first clock distribution buffer such that the incident signal propagates along the length of the transmission line from the first end to the second end; and a second clock distribution buffer having an input node and an output node, the input node being coupled to the second end of the transmission line, the second clock distribution buffer being operable to produce an output signal at the output node thereof from the incident signal on the input node thereof, where a first reflected signal is produced at the input node thereof and propagates along the length of the transmission line from the second end toward the first end.
The length of the transmission line preferably has a value such that a combined voltage level of the incident signal and the first reflected signal at the second end of the transmission line does not exceed about a maximum voltage level. The transmission line has a characteristic impedance (Z0) and a resistance (R), the output node of the first clock distribution buffer has an output impedance (Zs), the first and second clock distribution buffers have a supply voltage Vdd, and the maximum voltage level may be expressed substantially as:
Vdd* [Z0/(Z0+Zs)]. 
The first and second clock distribution buffers may have a supply voltage, and the maximum voltage level is preferably about equal to the supply voltage.
The incident signal at the second end of the transmission line preferably has a voltage level that is at least about one-fourth of the maximum voltage level. The voltage level of the incident signal is preferably between about one-fourth of the maximum voltage level and about one-half of the maximum voltage level.
The transmission line may include one or more of strip lines, stacked-pair lines, double-sided stacked-pair lines, double-sided stacked-pair lines with a lateral return path, micro-strip lines and groove lines. The transmission line, first clock distribution buffer and second clock distribution buffer are preferably part of a clock distribution architecture, such as an H-tree, an X-tree and/or an RC-balanced architecture.
The input clock signal preferably comprises a narrow pulse.
In accordance with one or more further aspects of the present invention, the length of the transmission line may have a value such that the incident signal exceeds a minimum threshold voltage of the input node of the second clock distribution buffer. Preferably, the minimum threshold voltage is at least about one-fourth of a maximum voltage level. The first and second clock distribution buffers may have a supply voltage, and the maximum voltage level may be substantially equal to the supply voltage. The incident signal may be between about one-fourth the maximum voltage level and about one-half the maximum voltage level.
In accordance with one or more further aspects of the present invention, the output node may have an output impedance (Zs), the length of the transmission line may have a characteristic impedance (Z0) and a resistance (R), and the length of the transmission line preferably exceeds a minimum length (d1), where the minimum length may be expressed as:
d1=2*(Z0/R)ln[(2*Z0)/(Z0+Zs)]. 
Preferably, the length of the transmission line is less than a maximum length (d2), and the maximum length may be expressed substantially as:
d2=2*(Z0/R)ln[(4*Z0)/(Z0+Zs)]. 
The incident signal may have a rise time (Trf), the length of the transmission line may have an inductance (L) and a capacitance (C), and the rise time is preferably limited in a way that may be expressed substantially by:
Trf less than 2{square root over (LC)}*(Z0/R)ln[4*Z0/(Z0+Zs)]. 
In accordance with one or more further aspects of the invention, the length of the transmission line preferably does not exceed a maximum length (d2), where the maximum length may be expressed substantially by:
d2=2*(Z0/R)ln[(4*Z0)/(Z0+Zs)]. 
In accordance with one or more further aspects of the present invention, a method of distributing clock signals along a transmission line of an integrated circuit having first and second ends defining a length, receiving an input clock signal at an input node of a first clock buffer; producing an incident signal at an output node of the first clock buffer based upon the input clock signal, the output node being coupled to the first end of the transmission line; and transmitting the incident signal along the transmission line from the first end to the second end, the second end being coupled to an input node of a second clock buffer, the second clock buffer being operable to produce an output signal on an output node thereof from the incident signal on the input node thereof, wherein the length has a value such that a combined voltage level of the incident signal and a first reflected signal at the second end of the transmission line does not exceed a maximum voltage level.
The transmission line preferably has a characteristic impedance (Z0) and a resistance (R), the output node of the first clock buffer preferably has an output impedance (Zs), the first and second clock buffers have a supply voltage Vdd, and the maximum voltage level may be expressed substantially as:
Vdd* [Z0/(Z0+Zs)]. 
The length of the transmission line preferably exceeds a minimum length (d1), where the minimum length may be expressed substantially as:
d1=2*(Z0/R)ln[(2*Z0)/(Z0+Zs)]. 
The length of the transmission line is preferably less than a maximum length (d2), where the maximum length may be expressed substantially as:
d2=2*(Z0/R)ln[(4*Z0)/(Z0+Zs)]. 
The incident signal may have a rise time (Trf) the length of the transmission line may have an inductance (L), a capacitance (C), a characteristic impedance (Z0) and a resistance (R), the output node of the first clock buffer may have an output impedance (Zs), and the rise time may be limited in a way that may be expressed substantially by:
Trf less than 2{square root over (LC)}*(Z0/R)ln[4*Z0/(Z0+Zs)]. 
Other features and advantages of the present invention will become apparent in light of the description herein taken in combination with the accompanying drawings.